EV71YEM1GE2014-BA0醫(yī)療設(shè)備
    發(fā)布者:lingliang  發(fā)布時間:2023-02-03 16:22:13  訪問次數(shù):217

          CLK_IN input frequency must be in the range 5 to 60 MHz. Out of this range, the performances may be decreased. In case of multi-cameras synchronization (means more than one camera on one acquisition board):

          ? the "master" camera will provide DATA, STROBE and LVAL signals to the acquisition board. The others will only provide DATA.

          ? the external clock CLK_IN must be input on each cameras to guaranty perfect data synchronization. 

          ? the trigger(s) input (TRIG1 and/or TRIG2) must be input on each cameras. It is recommended to synchronize the rising edge of these signals on the CLK_IN falling edge.

          ? cables must be balanced between each cameras (same quality, same length) to ensure perfect cameras synchronization.

          ? the CLK_IN frequency must be equal to the two CCD register frequency. It means that the user shall use either H=2 (2 taps at CLK_IN data rate) or H=10 (1 tap at 2xCLK_IN data rate). Using H=1 clock mode will provide LVAL jitter on the "slave" camera.

         ? Only "triggered and integration time controlled" (M=3 or M=4) can be used. These modes ensure perfect readout phase starting for each cameras.

         Signal Name I/O Type Description TRIG1 I RS644 CC1 – Synchronization input (refer to “Synchronization Mode” on page 6) TRIG2 I RS644 CC2 – Start Integration period in dual synchro mode (refer to “Synchronization Mode” on page 6) CLK_IN I RS644 CC4 – External clock for (multi-)camera synchronization (refer to “Synchronization Mode” on page 6

         Signal Name I/O Type Description ODD[11-0] O RS644 Odd pixel data (refer to “Output Data Timing” on page 8), ODD-00 = LSB, ODD-11 = MSB EVEN[11-0] O RS644 Even pixel data (refer to “Output Data Timing” on page 8), EVEN-00 = LSB, EVEN-11 = MSB STROBE O RS644 Output data clock (refer to “Output Data Timing” on page 8), data valid on the rising edge LVAL O RS644 Line valid (refer to “Output Data Timing” on page 8), active high signa

         The Camera Link interface provides two LVDS signal pairs for the communication between the camera and the frame grabber. This is an asynchronous serial communication based on RS-232 protocol. The configuration of the serial line is: ? Full duplex/without handshaking ? 9600 bauds, 8-bit data, no parity bit, 1 stop bit

         mmand Syntax The valid syntax is "S = n(CR)" with: ? S: command identification as per “Camera Command and Control” on page 5. S is a single character in upper case. ? n: setting value. ? (CR): means "carriage return". no space, nor tab may be inserted between S, =, n and (CR). Example of a valid command: ? G = 3(CR): sets the camera to gain 3 (refer to “Camera Command and Control” on page 5 for exact value calculation). Example of non valid commands: ? G = 3(CR): spaces ? g = 3(CR): g instead of G ? G = 1040(CR): 1040 is outside of range

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